This invention generally pertains to, but is not limited to, multibranch feedforward linearizers for amplifiers, for example, RF power amplifiers used in wireless communication systems.
The operation of the multibranch feedforward linearizer shown in FIG. 1 can be described in terms of two circuits: a signal cancellation circuit 101 and a distortion cancellation circuit 102. When an adjuster circuit s 110 in the signal cancellation circuit 101 is set optimally, a linear estimate of the signal at the output of the power amplifier 103 is generated by the signal circuit cancellation paths and subtracted from the distorted power amplifier signal, vpa. The residual error signal from the signal cancellation circuit, ve, output from the subtractor 106, is the power amplifier distortion signal. (As will be appreciated by those skilled in the art, the elements shown in FIG. 1 as pickoff points and the elements shown as adders and subtractors may be implemented by directional couplers, splitters or combiners, as appropriate.)
The distortion cancellation circuit 102 subsequently adjusts the phase and amplitude of the distortion signal ve by adjuster circuit d 111 and error amplifier 108 to subtract it using subtractor 107 from the nonlinear output signal vbr, output from the delay line 112. This reduces the distortion in the final output signal (vo) from the linearized amplifier. The desired output takes the role of an xe2x80x9cerror signalxe2x80x9d in the distortion cancellation circuit 102. The level of distortion cancellation at the output of the linearized amplifier depends on how accurately adjuster circuits s 110 and d 111 are set, and how well those adjuster circuits track changes in the linearizer.
A notable variant of the multibranch feedforward linearizer is to place adjuster circuit s 109 in series with the power amplifier, as shown in FIG. 3, and to replace the adjuster circuit s 110 with a delay line 118. In this configuration, any additional distortion generated by adjuster circuit s 109 is cancelled by the feedforward linearizer. The hardware or software used to set the parameters of the adjuster circuits 109, 110, and 111 are the subject of this invention.
The degree of distortion cancellationxe2x80x94its depth and bandwidthxe2x80x94at the output of the linearized amplifier depends on the structure of adjuster circuits s 110 (or 109) and d 111. A general implementation of the adjuster circuit s 110 for a multibranch feedforward linearizer includes M parallel circuit branches summed by combiner 206 as shown in FIG. 2. Similarly, for adjuster circuit d 111, N parallel circuit branches are summed by a combiner 216 (see FIG. 6). In a single branch feedforward linearizer, the adjuster circuits s and d both have a single branch (M=1 and N=1, respectively), while at least one adjuster circuit in a multibranch linearizer has two or more branches, as shown in the examples of FIGS. 2 and 6. Each circuit branch of the adjuster circuit s shown in FIG. 2 has a linear filter element (200, 202, 204) with a frequency response haj(f) (j=1 to M) in series with a complex gain adjuster (CGA) (201, 203 and 205). Similarly, each circuit branch of the adjuster circuit d shown in FIG. 6 has a linear filter element (210, 212, 214) with a frequency response hbj(f) (j=1 to N) in series with a CGA (211, 213 and 215). The linear filter elements haj(f) and hbj(f) could be as simple as a delay or as complicated as a general linear filter function.
A multibranch feedforward linearizer has a significantly larger linearization bandwidth than a single branch feedforward linearizer, and the linearization bandwidth depends on the number of parallel branches in the adjuster circuits s 110 (or 109) and d 111. Single branch feedforward linearizers and multibranch feedforward linearizers are described in U.S. Pat. Nos. 5,489,875 and 6,208,207, both of which are incorporated by reference.
The CGAs in each branch of the adjuster circuit control the amplitude and phase of the signal in each branch. Two examples of CGA configurations are shown in FIGS. 4 and 5. The implementation shown in FIG. 4 uses polar control parameters GA and GB, where GA sets the amplitude of the attenuator 401, while GB sets the phase of the phase shifter 402. The implementation shown in FIG. 5 uses Cartesian control parameters, also designated GA and GB, where GA sets the real part of the complex gain, while GB sets the imaginary part of the complex gain. In this implementation, the input signal I is split into two signals by splitter 506, one of which is then phase-shifted by 90 degrees by phase shifter 503, while the other is not. After GA and GB are applied by mixers or attenuators 505 and 504 respectively, the signals are summed by combiner 507 to produce the CGA output signal O. U.S. Pat. No. 6,208,207 describes the use of linearization of these mixers and attenuators, so that desired values of complex gain can be obtained predictably by appropriate setting of the control voltages GA and GB.
A multibranch feedforward linearizer with M CGAs in the adjuster circuit s 110 of the signal cancellation circuit 101 and N CGAs in the adjuster circuit d 111 of the distortion cancellation circuit 102 is shown in FIG. 6. In this linearizer, an adaptation controller 114 computes the parameters a1 through aM of the CGAs of the adjuster circuit s 110 and the parameters b1 through bN of the CGAs of the adjuster circuit d 111, by monitoring internal signals of the adjusters s 110 and d 111, and the error signal, ve, and the output signal, vo. The internal signals of the adjusters s 110 and d 111 are respectively va1 through vaM and vb1 through vbN. The actual signals monitored by the adaptation controller are, however, vam1 through vamM and vbm1 through vbmN, wherein the difference between these internal signals and the monitored signals is respectively represented by observations filters ham1(f) through hamM(f) (601, 602, 603) and hbm1(f) through hbmN(f) (605, 606, 607). Further, the respective differences between the error and output signals, ve and vo, and the monitored error and output signals, vem and vom, can be represented by observation filters hem(f) (604) and hom(f) (608). The differences between the internal (or error and output) signals and the monitored signals are gain and phase changes therebetween caused by hardware implementation of the signal lines and monitoring components, e.g., cables, circuit board traces, mixers, filters and amplifiers. As represented by the observation filters, these gain and phase changes may be frequency dependent. Calibration methods for relating the internal, error and output signals to their monitored counterparts are discussed below.
The nonlinear power amplifier in the circuit is linearized by adjusting the M CGAs in the signal cancellation circuit and the N CGAs in the distortion cancellation circuit to optimal values via the adaptation controller. There are many different algorithms available for adjusting the CGAs in the feedforward circuit, but the complexity and rate of convergence vary significantly depending on what signals are monitored in the circuit. For example, an adaptation controller 714, as shown in FIG. 7, monitors only the output error signals (ve and vo) for the signal and distortion cancellation circuits to generate control signals a and b. Known optimization algorithms, such as the Nelder-Mead (NM) simplex algorithm, the Davidon-Fletcher-Powell (DFP) algorithm, or those set forth in U.S. Pat. No. 5,489,875, operate to minimize the power in the associated error signal, but they are slow to converge. For example, in the DFP algorithm, the first derivatives of the signal cancellation circuit function are estimated with perturbations. Perturbations are deliberate misadjustment of the CGAs and used to estimate the local gradient of the circuit, but the perturbations add jitter to the output error signal and are numerically intensive. The number of misadjustments to calculate each update in the algorithm grows rapidly as the number of branches in the complex gain adjuster grows. For such reasons, adaptation methods that monitor only the error signal (ve or vo) are slow to converge.
Substantially faster convergence can be obtained by monitoring additional signals in the circuit and employing algorithms that compute correlations among them and the error signals. An example of such correlation-based algorithms is least mean squared (LMS) as described in U.S. Pat. No. 5,489,875. Faster convergence is obtained in the case of multibranch adjusters by correlation-based algorithms like decorrelated LMS (DLMS), least squares (LS) and recursive LS (RLS). (The mention of the DLMS, LS and RLS algorithms in this Background Section is not intended to imply that they are prior art to the present invention.)
FIG. 8 shows an example of a multibranch feedforward circuit where internal branch signals labelled as vam and vbm are monitored by adaptation controller 814 as well as the error signals ve and vo to generate control signals a and b. The internal signals correspond to the signals in the adjuster circuits, similar to va1 through vaM shown in FIG. 2 or vb1 through vbN shown in FIG. 6. In FIG. 8, a stroke through the monitor lines vam and vbm from adjuster circuits s and d means that a group of M or N signals are monitored respectively. An example of a prior art feedforward linearizer with branch monitors can be found in U.S. Pat. No. 5,489,875.
The branch monitor is a narrowband receiver that selectively samples a portion of the input power spectrum. The receiver is agile and, by programming different local oscillator frequencies, different portions of the power spectrum are selectively sampled. FIG. 9 shows an example of a monitor receiver block diagram. The monitor is frequency selective and the frequency (f1) sampled by the analog to digital converter (ADC) depends on the local oscillator frequencies fLO1 and fLO2. The frequency selectivity of the monitor branches is explicitly noted by including the variable fi in signal names. The input to the branch monitor receiver is first amplified by low noise amplifier 901, and is then down-converted by down converters 902 and 903, although more or fewer stages of downconversion may be appropriate, depending on the application. The down-converted signal is then digitized by the ADC 904 to generate vamj(f1). Down converter 902 (903) include mixer 910 (920) having a mixing signal generated by local oscillator frequency 913 (923) at frequency fLO1 (fLO2). The output of the mixer 910 (920) is bandpass filtered by bandpass filter 911 (921) followed by amplifier 912 (922).
Branch monitor receivers can be used together to form partial correlations over a portion of the input power spectrum. FIG. 10 shows a partial correlator, in which local oscillators 1001 and 1002 select the frequency of the partial correlation. Frequency shifting and bandpass limitation are performed by the mixer/bandpass filter combinations 1003/1007, 1004/1008, 1005/1009, and 1006/1010. The signals output by the bandpass filters 1009 and 1010 are digitally converted, respectively, by analog-to-digital converters (ADCs) 1011 and 1012. Those digital signals are bandpass correlated by digital signal processor (DSP) 1013 to produce the real and imaginary components of the partial correlation. (See, for example, FIG. 9 of U.S. Pat. No. 5,489,875 for a description of the operation of a partial correlator similar to that shown in FIG. 10 herein.)
Although correlation-based algorithms are well suited to adapting multibranch feedforward circuits, one of their drawbacks is the requirement of a separate branch monitor to sample each of the M and N internal adjuster signals, as well as the error signal, in contrast to the less efficient power minimization algorithms which require only an error signal monitor. That is, a branch monitor is required for each of the M and N branches in the adjuster circuits.
Accordingly, there is a need for a reduced architecture which requires only a single monitor receiver for each of the signal cancellation and distortion cancellation circuits, irrespective of the number of branches in each of those circuits. Such a reduced architecture would result in a significant savings in cost, because, as noted above, branch monitors contain many components.
In one aspect of the present invention, an amplifier linearizer circuit has a signal cancellation circuit including a signal adjuster having M branch signals (Mxe2x89xa71), and a distortion cancellation circuit including a signal adjuster having N branch signals (Nxe2x89xa71). The linearizer has a controller for adaptively controlling the M-branch and N-branch signal adjusters. The controller has only one monitor receiver to monitor the M branch signals and only one monitor receiver to monitor the N branch signals.
This and other aspects of the present invention may be ascertained from the detailed description of the preferred embodiments set forth below, taken in conjunction with one or more of the following drawings.